The semiconductor industry has had tremendous success in delivering ever more cost effective chips to market through the use of scaling. However, while scaling works well in device or front-end semiconductor processing, device wiring is not amenable to scaling and results in degraded interconnect resistance and/or capacitance. To alleviate this problem, the industry has been migrating to the use of a lower resistance conductor, such as copper (Cu), and is also introducing lower-k (k=dielectric constant) insulators to reduce capacitance in damascene interconnect structures. Newly developed insulators in the ultra-low-k (ULK) range (k<2.5) are generally characterized by a great deal of porosity (e.g., 30-50%). These materials are extremely fragile and difficult to integrate since they are susceptible to contamination from other sources.
In a dual-damascene (DD) structure, a single metal deposition step is used to simultaneously form Cu metal lines and vias. The Cu metal lines and vias are formed by filling recessed features, such as a trench, a via, or other interconnect structure, in a dielectric film or substrate. After filling, the excess Cu metal that is deposited outside the recessed feature is removed by a chemical-mechanical polishing (CMP) process, thereby forming a planar structure with metal interconnect inlays.
The electrical current density in an integrated circuit's interconnects significantly increases for each successive technology node due to decreasing minimum feature sizes. Because electromigration (EM) and stress migration (SM) lifetimes are inversely proportional to current density, EM and SM have fast become critical challenges. EM lifetime in Cu dual damascene interconnect structures is strongly dependent on atomic Cu transport at the interfaces of bulk Cu metal and surrounding materials which is directly correlated to adhesion at these interfaces. New materials that provide better adhesion and better EM lifetime have been studied extensively. For example, a cobalt-tungsten-phosphorus (CoWP) layer has been selectively deposited on bulk Cu metal using an electroless plating technique. The interface of CoWP and bulk Cu metal has superior adhesion strength that yields longer EM lifetime. However, maintaining acceptable deposition selectivity on bulk Cu metal, especially for tight pitch Cu wiring, and maintaining good film uniformity, has affected acceptance of this complex process. Furthermore, wet process steps using acidic solution may be detrimental to the use of CoWP.